The escalating requirements for high-density and performance associated with ultra large-scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance-capacitance) interconnection pattern, particularly where sub-micron via contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed dielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines may be formed on top of a substrate or in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor "chips" comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to sub-micron levels.
In efforts to improve the operating performance of a chip, low k dielectric materials have been increasingly investigated for use as replacements for dielectric materials with high k (i.e. dielectric constant values). Lowering the overall k values of the dielectric layers employed in the metal interconnect layers lowers the RC-delay of the chip and improves its performance. However, low k materials, such as benzocyclobutene (BCB), hydrogen silsesquioxane (HSQ), SiOF, and the material sold under the tradename of FLARE, are often more difficult to handle than traditionally employed higher k materials, such as silicon dioxide. For example, when traditional methods of patterning dielectrical layers are employed, special steps must be taken to protect the low k dielectric layer material from unintended etching. For example, a photoresist layer that is used to pattern a low k dielectric layer is usually removed by oxygen ashing or solvents. However, this type of removal of the photoresist layer also typically reacts with the low k dielectric layer to undesirably remove some of or chemically alter the low k dielectric layer. To prevent this occurrence, a capping layer made of a different material than the low k dielectric layer is employed to protect the low k dielectric layer in subsequent processing steps, such as etching.
The formation of such a bilayer interlayer dielectric as described above (i.e., a low k dielectric layer and a capping layer) has some attendant difficulties. More particularly, as described below with respect to FIGS. 1-3 depicting a prior art process of forming a bilayer interlayer dielectric, it is difficult to achieve a consistent composite dielectric constant for the interlayer dielectric. This leads to differences in circuit speed and clock skew.
In FIG. 1, the semiconductor wafer 10, during a stage of manufacturing, has a substrate 12 upon which conductive material (e.g., a metal) is patterned. This pattern may be created, for example, by deposition of a metal, such as aluminum or copper, followed by a patterning and etching away of the metal to leave metal lines and other structures that are desired. Over the surface of the substrate 12, the metal exhibits different pattern densities. For example, a single metal line 14 is depicted on the left hand side of FIG. 1. A somewhat more dense pattern of metal is represented by reference numeral 16. A wide metal or dense metal pattern is depicted with reference numeral 18 on the right hand side of FIG. 1. These patterns represent different areas of the semiconductor device provided on the semiconductor wafer 10.
A first dielectric layer 20 is then spin-coated on the substrate 12 in a non-conformal manner to completely cover the metal regions 14, 16 and 18. Examples of suitable low k material (i.e. k less than 4) include HSQ, FLARE, BCB and others. As can be seen from the schematic depiction of FIG. 2, the thickness of the spun-on low k dielectric layer 20 varies systematically across the metal pattern as a function of the local pattern density of the metal. Hence, the thickness of the low k dielectric layer 20 is much greater over the wide metal (densest) pattern region 18, and thinner over the less dense metal regions 14 and 16. This variation in the thickness of the non-conformally spun-on low k dielectric layer 20 over different pattern density regions is a characteristic of this class of dielectric materials and the spinning-on process.
When a capping layer 22, such as an oxide, is deposited over the low k dielectric layer 20 as depicted in FIG. 3, and subsequently planarized as normally done in semiconductor processing, the relative thicknesses of the low k dielectric layer 20 and the capping layer 22 varies systematically due to the pattern density effects. For example, in the right hand side of FIG. 3, the ratio of the thickness of the low k dielectric layer 20 to the thickness of the capping layer 22 is much greater over the dense metal region 18 than over the less dense regions 14 and 16. Due to the relatively greater amount of low k material in this region 18 relative to the higher k material in the capping layer 22, the composite dielectric constant in the dense metal region 18 will be lower than in the less dense metal regions 14, 16.
The variation in the composite dielectric value over the integrated circuit has an effect on the RC in the different locations of the circuit. For example, in the dense metal regions 18 where the composite dielectric constant is lower, the RC will also be lower and the circuit will be faster than in the less dense metal regions 14, 16, where the composite dielectric constant for the interlayer dielectric is greater. These different circuit speeds over a device create clock skew in the device.
There is a need for a bilayer interlayer dielectric that achieves the advantages of reducing the overall dielectric constant of an interlayer dielectric by employing low k materials, but avoids the creation of clock skew in a device that results from differences in circuit speed.